Nano-Electro-Mechanical (NEM) Relay Devices and Technology for Ultra-Low Energy Digital Integrated Circuits

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Complementary-Metal-Oxide-Semiconductor (CMOS) technology scaling has brought about an integrated circuits (IC) revolution over the past 40+ years, due to dramatic increases in IC functionality and performance, concomitant with reductions in cost per function. In the last decade, increasing power density has emerged to be the primary barrier to continued rapid advancement in IC technology, fundamentally due to non-zero transistor off-state leakage. While innovations in materials, transistor structures, and circuit/system architecture have enabled the semiconductor industry to continue to push the boundaries, a fundamental lower limit in energy per operation will eventually be reached. A more ideal switching device with zero off-state leakage becomes necessary. This dissertation proposes a solution to the CMOS power crisis via mechanical computing. Specifically, robust electro-mechanical relay technologies are developed for digital circuit application. A 4-Terminal (4T) relay design is firstly developed. Key technology features include tungsten contacts for high endurance; low-thermal-budget p +-poly-Si 0.4 Ge 0.6 structure for post-CMOS process compatibility; Al 2 O 3 as a reliable insulation material; dry release step to mitigate stiction; and folded-flexure design to mitigate the impact of residual stress. Fabricated relays show good conductance (R ON < 10 kΩ), abrupt switching behavior (sub-threshold swing below 0.1 mV/dec), and virtually zero leakage (I OFF ~ 10-14 A). Switching delay in the 100 ns range and endurance exceeding 10 9 on/off cycles is achieved with excellent device yield (> 95%). With relay design and process optimizations, pull-in voltage below 10 V with less than 1 V hysteresis is achieved. Miniaturization reduces the device footprint to 35μm×50μm, ~10% of the first generation device footprint (120μm×150μm). Relays with multiple source/drain electrodes and multiple gate electrodes are proposed for increased circuit functionality and reduced device count. Finally, simple relay-based logic circuits are demonstrated to show pathways to relay-based digital integrated circuits. The complementary inverter is the basis for all digital logic circuits and is investigated in depth. Relay-based logic gates are demonstrated using CMOS-like and relay-specific design approaches. Multi-input/multi-output relays are proposed to enable any …